By Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto
Analog Circuit layout comprises the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and precious layout principles within the sector of analog circuit layout. each one half is gifted by way of six specialists in that box and state-of-the-art info is shared and overviewed. This e-book is quantity 20 during this profitable sequence of Analog Circuit layout, offering necessary info and ideal overviews of:
Topic 1 : Low Voltage Low energy, chairman: Andrea Baschirotto
Topic 2 : brief variety instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational assurance additionally makes it compatible to be used in a complicated layout direction.
Read or Download Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC PDF
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Additional resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC
H. , A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27(3), 351–358 (1992) 5. B. Murmann, ADC performance survey 1997–2011, [Online]. stanford. html 6. A. , A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuits 45(12), 2602–2612 (2010) 7. J. , Low-power pipeline ADC for wireless LANs. IEEE J. Solid-State Circuits 39(8), 1338–1340 (2004) 8. S. 11 g WLAN SoC, in ISSCC Digest Technical Papers, San Francisco, Feb, 2005, pp.
In light of this discussion, Sect. 5 compares the state-of-the art with practical limits on power dissipation and Sect. 6 ends this chapter with a summary. 2 shows a conceptual block diagram of the pipelined A/D converter topology. Several converter stages are cascaded and process the analog input sequentially, similar to flip-flops propagating a bit stream in a digital shift register. Each stage samples and holds its analog input (through S/H circuits implicitly contained in the local A/D block and the summing node) and performs a coarse A/D conversion.
Solid-State Circuits 44(9), 2366–2380 (2009) 62. M. , A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J. Solid-State Circuits 41(11), 2417–2423 (2006) 38 B. Murmann 63. B. E. Boser, Digital domain measurement and cancellation of residue amplifier nonlinearity in pipelined ADCs. IEEE Trans. Instrum. Meas. 56(6), 2504–2514 (2007) 64. J. -K. Moon, Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Trans. Circuits Syst. II 50(9), 531–538 (2003) 65.